KR20120059398A
|
|
Multiple level spine routing
|
US2009235219A1
|
|
Hierarchical analog IC placement subject to symmetry, matching and proximity constraints
|
US2009178013A1
|
|
System for implementing post-silicon IC design changes
|
US2009031269A1
|
|
Hierarchy-based analytical placement method for an integrated circuit
|
US2009113367A1
|
|
Analog IC placement using symmetry-islands
|
US2007288878A1
|
|
Template-based gateway model routing system
|
US7917881B1
|
|
Timing of a circuit design
|
US2007256045A1
|
|
V-shaped multilevel full-chip gridless routing
|
US2007174805A1
|
|
Debugging system for gate level IC designs
|
US2007106488A1
|
|
Incremental circuit re-simulation system
|
US2009222774A1
|
|
Method for evaluating the quality of a computer program
|
US2007266351A1
|
|
Method and system for evaluating computer program tests by means of mutation analysis
|