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Multi-thread processor with multi-bank branch-target buffer
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Micro-op fusion for non-adjacent instructions
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Single-thread processing of multiple code regions
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Processor with efficient reorder buffer (rob) management
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Single-thread speculative multi-threading
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Memory access control for parallelized processing
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Hardware-based run-time mitigation of conditional branches
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Flushing in a parallelized processor
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Processor with effective memory access
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Sequential monitoring and management of code segments for run-time parallelization
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Speculative multi-threading trace prediction
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Hardware-based run-time mitigation of conditional branches
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Early termination of segment monitoring in run-time code parallelization
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Parallel execution based on the command sequence monitored in advance
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Run-time code parallelization with continuous monitoring of repetitive instruction sequences
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Run-time code parallelization with independent speculative committing of instructions per segment
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Run-time code parallelization using out-of-order renaming with pre-allocation of physical registers
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Processor with efficient processing of recurring load instructions
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Processor with efficient processing of recurring load instructions from nearby memory addresses
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Processor with efficient memory access
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