Learn more

FLACHOWSKY STEFAN

Overview
  • Total Patents
    39
About

FLACHOWSKY STEFAN has a total of 39 patent applications. Its first patent ever was published in 2010. It filed its patents most often in United States. Its main competitors in its focus markets semiconductors are SHANGHAI GEYI ELECTRONIC CO LTD, USAMI TATSUYA and QUANTUM WAFER INC.

Patent filings in countries

World map showing FLACHOWSKY STEFANs patent filings in countries
# Country Total Patents
#1 United States 39

Patent filings per year

Chart showing FLACHOWSKY STEFANs patent filings per year from 1900 to 2020

Focus industries

# Industry
#1 Semiconductors

Focus technologies

# Technology
#1 Semiconductor devices

Top inventors

# Name Total Patents
#1 Flachowsky Stefan 39
#2 Hoentschel Jan 25
#3 Scheiper Thilo 18
#4 Illgen Ralf 9
#5 Mikalo Ricardo P 5
#6 Javorka Peter 3
#7 Wirbeleit Frank 2
#8 Kessler Matthias 2
#9 Langdon Steven 2
#10 Kronholz Stephan-Detlef 2

Latest patents

Publication Filing date Title
US2014042550A1 Integrated circuits with improved spacers and methods for fabricating same
US2014030876A1 Methods for fabricating high carrier mobility finfet structures
US2014015060A1 Stress enhanced CMOS circuits and methods for their manufacture
US2014015055A1 Replacement gate FinFET structures with high mobility channel
US8598007B1 Methods of performing highly tilted halo implantation processes on semiconductor devices
US2013302956A1 Methods of forming semiconductor devices with embedded semiconductor material as source/drain regions using a reduced number of spacers
US2013267078A1 Processes for preparing stressed semiconductor wafers and for preparing devices including the stressed semiconductor wafers
US2013244437A1 Methods of forming features on an integrated circuit product using a novel compound sidewall image transfer technique
US2013196495A1 Methods for fabricating MOS devices with stress memorization
US2013175610A1 Transistor with stress enhanced channel and methods for fabrication
US2013178024A1 In situ doping and diffusionless annealing of embedded stressor regions in PMOS and NMOS devices
US2013178034A1 Methods of making transistor devices with elevated source/drain regions to accommodate consumption during metal silicide formation process
US2013175545A1 Semiconductor device with strain-inducing regions and method thereof
US2013157421A1 Methods for the fabrication of integrated circuits including back-etching of raised conductive structures
US2013146976A1 Integrated circuits formed on strained substrates and including relaxed buffer layers and methods for the manufacture thereof
US2013105885A1 Canyon gate transistor and methods for its fabrication
US2013095627A1 Methods of Forming Source/Drain Regions on Transistor Devices
US2013069111A1 Strained semiconductor devices having asymmetrical heterojunction structures and methods for the fabrication thereof
US2013065373A1 Methods and Systems for Forming Implanted Doped Regions for a Semiconductor Device Using Reduced Temperature Ion Implantation
US2013065367A1 Methods of Forming Highly Scaled Semiconductor Devices Using a Reduced Number of Spacers