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DOYLE BRIAN S

Overview
  • Total Patents
    35
  • GoodIP Patent Rank
    208,985
About

DOYLE BRIAN S has a total of 35 patent applications. Its first patent ever was published in 2004. It filed its patents most often in United States and WIPO (World Intellectual Property Organization). Its main competitors in its focus markets semiconductors, computer technology and electrical machinery and energy are RAMASWAMY D V NIRMAL, HERNER SCOTT BRAD and BHATTACHARYYA ARUP.

Patent filings in countries

World map showing DOYLE BRIAN Ss patent filings in countries

Patent filings per year

Chart showing DOYLE BRIAN Ss patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Doyle Brian S 35
#2 Shah Uday 15
#3 Chau Robert S 14
#4 Kuo Charles C 12
#5 Datta Suman 12
#6 Somasekhar Dinesh 7
#7 Oguz Kaan 7
#8 Kencke David L 6
#9 Doczy Mark L 6
#10 Kavalieros Jack T 6

Latest patents

Publication Filing date Title
US2015091058A1 Vertical transistor devices for embedded memory and logic technologies
US2014177326A1 Electric field enhanced spin transfer torque memory (STTM) device
US2014175583A1 Perpendicular spin transfer torque memory (STTM) device having offset cells and method to form same
US2014175575A1 Perpendicular spin transfer torque memory (STTM) device with enhanced stability and method to form same
US2014166981A1 Vertical nanowire transistor with axially engineered semiconductor and gate metallization
US2014160628A1 Structure to make supercapacitor
US2012326274A1 Semiconductor structure having an integrated quadruple-wall capacitor for embedded dynamic random access memory (eDRAM) and method to form the same
US2012235274A1 Semiconductor structure having an integrated double-wall capacitor for embedded dynamic random access memory (edram) and method to form the same
US2012153412A1 Write current reduction in spin transfer torque memory devices
US2010155801A1 Integrated circuit, 1T-1C embedded memory cell containing same, and method of manufacturing 1T-1C memory cell for embedded memory application
US2009206405A1 Fin field effect transistor structures having two dielectric thicknesses
US2009108313A1 Reducing short channel effects in transistors
US2009057846A1 Method to fabricate adjacent silicon fins of differing heights
US2009004868A1 Amorphous silicon oxidation patterning
US2009001438A1 Isolation of MIM FIN DRAM capacitor
US2008237672A1 High density memory
US2008237719A1 Multi-gate structure and method of doping same
US2008157162A1 Method of combining floating body cell and logic transistors
US2007235763A1 Substrate band gap engineered multi-gate pMOS devices
US2007090416A1 CMOS devices with a single work function gate electrode and method of fabrication