US2014038085A1
|
|
Automatic misalignment balancing scheme for multi-patterning technology
|
US2014028407A1
|
|
Reconfigurable and auto-reconfigurable resonant clock
|
US2013342247A1
|
|
Capactive load PLL with calibration loop
|
US8432204B1
|
|
Current-controlled oscillator (CCO) based PLL
|
US2013126979A1
|
|
Integrated circuits with electrical fuses and methods of forming the same
|
US2013082754A1
|
|
Phase locked loop calibration
|
US2012266126A1
|
|
Systems and methods of designing integrated circuits
|
US2012230457A1
|
|
Clock and data recovery using LC voltage controlled oscillator and delay locked loop
|
US2012217586A1
|
|
Integrated circuits with resistors and methods of forming the same
|
US2012050930A1
|
|
VOL up-shifting level shifters
|
US2012044008A1
|
|
Level shifters having diode-connected devices for input-output interfaces
|
US2012019302A1
|
|
Low minimum power supply voltage level shifter
|
US2011267107A1
|
|
Circuit for reducing negative bias temperature instability
|
US2010271246A1
|
|
Providing linear relationship between temperature and digital code
|
US2011199063A1
|
|
Integrated circuits including an LC tank circuit and operating methods thereof
|
US2010223585A1
|
|
Dummy fill to reduce shallow trench isolation (STI) stress variation on transistor performance
|