Learn more

CHEN SHIH-HUNG

Overview
  • Total Patents
    38
About

CHEN SHIH-HUNG has a total of 38 patent applications. Its first patent ever was published in 2005. It filed its patents most often in United States. Its main competitors in its focus markets semiconductors, computer technology and machines are YANGTZE MEMORY TECHNOLOGIES CO LTD, PARK NAM KYUN and KATSUMATA RYOTA.

Patent filings in countries

World map showing CHEN SHIH-HUNGs patent filings in countries
# Country Total Patents
#1 United States 38

Patent filings per year

Chart showing CHEN SHIH-HUNGs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Chen Shih-Hung 38
#2 Lue Hang-Ting 15
#3 Shih Yen-Hao 6
#4 Hsieh Kuang-Yeu 4
#5 Xiao Ying 3
#6 Chen Yi-Chou 3
#7 Lin Chin-Hsiang 2
#8 Zhang Ying 1
#9 Hong Tian-Jue 1
#10 Lin Lo-Yueh 1

Latest patents

Publication Filing date Title
US8759217B1 Method for forming interlayer connectors to a stack of conductive layers
US2014177311A1 Memory device structure with decoders in a device level separate from the array level
US2014061947A1 Chip stack structure and manufacturing method thereof
US2014054535A1 Semiconductor structure with improved capacitance of bit line
US2014054784A1 Integrated circuit connector access region
US2014043067A1 Semiconductor structure and manufacturing method and operating method of the same
US2013334575A1 Damascene word line
US2013322990A1 Loadport bridge for semiconductor fabrication tools
US2013277799A1 Integrated circuit capacitor and method
US2013277852A1 Method for creating a 3D stacked multichip module
US2013264719A1 Semiconductor structure and method for manufacturing the same
US2013264683A1 Semiconductor structure and manufacturing method of the same
US2013245978A1 Systems and methods of controlling semiconductor wafer fabrication processes
US2013214340A1 Semiconductor structure and manufacturing method of the same
US2013175598A1 Damascene word line
US2013119455A1 NAND flash with non-trapping switch transistors
US2013075802A1 Contact architecture for 3D memory array
US2013075920A1 Stacked IC device with recessed conductive layers adjacent to interlevel conductors
US2013072013A1 Etching method and apparatus
US2012329308A1 Connector terminal