|
US2010044803A1
|
|
Sealing structure for high-K metal gate
|
|
US2007010073A1
|
|
Method of forming a MOS device having a strained channel region
|
|
US2006284249A1
|
|
Impurity co-implantation to improve transistor performance
|
|
US2006263992A1
|
|
Method of forming the N-MOS and P-MOS gates of a CMOS semiconductor device
|
|
US2006244074A1
|
|
Hybrid-strained sidewall spacer for CMOS process
|
|
US2006234455A1
|
|
Structures and methods for forming a locally strained transistor
|
|
US2006151808A1
|
|
MOSFET device with localized stressor
|
