CASCADE DESIGN AUTOMATION has a total of 13 patent applications. Its first patent ever was published in 1989. It filed its patents most often in United States, WIPO (World Intellectual Property Organization) and Canada. Its main competitors in its focus markets computer technology, basic communication technologies and semiconductors are CHENGDU BOYNN TIMES SOFTWARE CO LTD, RN2R L L C and SINGULAR COMPUTING LLC.
# | Country | Total Patents | |
---|---|---|---|
#1 | United States | 5 | |
#2 | WIPO (World Intellectual Property Organization) | 3 | |
#3 | Canada | 2 | |
#4 | EPO (European Patent Office) | 2 | |
#5 | Australia | 1 |
# | Industry | |
---|---|---|
#1 | Computer technology | |
#2 | Basic communication technologies | |
#3 | Semiconductors |
# | Technology | |
---|---|---|
#1 | Electric digital data processing | |
#2 | Pulse technique | |
#3 | Semiconductor devices | |
#4 | Static stores |
# | Name | Total Patents |
---|---|---|
#1 | Rossman Thomas F | 5 |
#2 | Jensen John S | 4 |
#3 | Fisher Louis C | 4 |
#4 | Buchanan Marc E | 3 |
#5 | Lippincott George P | 3 |
#6 | Farbarik Ray | 2 |
#7 | Nicholls William H | 2 |
#8 | You Yongtao | 1 |
#9 | Rossman Mark E | 1 |
#10 | Frazier Dean P | 1 |
Publication | Filing date | Title |
---|---|---|
WO9748061A1 | Method and apparatus for optimization of standard cell libraries | |
WO9642060A1 | Method and apparatus for point landmark design of integrated circuits | |
US5654898A | Timing-driven integrated circuit layout through device sizing | |
WO9522204A1 | High-speed solid state buffer circuit and method for producing the same | |
US5351197A | Method and apparatus for designing the layout of a subcircuit in an integrated circuit | |
US5210701A | Apparatus and method for designing integrated circuit modules | |
US5097422A | Method and apparatus for designing integrated circuits |