|
US2013339802A1
|
|
Dynamic hardware trace supporting multiphase operations
|
|
US2013173681A1
|
|
Range check based lookup tables
|
|
US2013173891A1
|
|
Convert from zoned format to decimal floating point format
|
|
US2013173892A1
|
|
Convert to zoned format from decimal floating point format
|
|
US2011320514A1
|
|
Decimal adder with end around carry
|
|
US2011320512A1
|
|
Decimal floating point mechanism and process of multiplication without resultant leading zero detection
|
|
US2011131266A1
|
|
Decimal floating point multiplier and design structure
|
|
US2010306632A1
|
|
Error detection using parity compensation in binary coded decimal and densely packed decimal conversions
|
|
US2009240753A1
|
|
Execution of fixed point instructions using a decimal floating point unit
|
|
US2009210659A1
|
|
Processor and method for workaround trigger activated exceptions
|
