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CAPITAL MICROELECTRONICS (BEIJING) TECH CO LTD

Overview
  • Total Patents
    27
  • GoodIP Patent Rank
    59,460
About

CAPITAL MICROELECTRONICS (BEIJING) TECH CO LTD has a total of 27 patent applications. Its first patent ever was published in 2014. It filed its patents most often in China. Its main competitors in its focus markets computer technology and basic communication technologies are SHOOLMAN YIFTACH, FAERBER FRANZ and CALPONT CORP.

Patent filings in countries

World map showing CAPITAL MICROELECTRONICS (BEIJING) TECH CO LTDs patent filings in countries
# Country Total Patents
#1 China 27

Patent filings per year

Chart showing CAPITAL MICROELECTRONICS (BEIJING) TECH CO LTDs patent filings per year from 1900 to 2020

Focus technologies

Top inventors

# Name Total Patents
#1 Liu Ming 8
#2 Liu Chengli 5
#3 He Ke 5
#4 Huang Pan 4
#5 Jiang Zhonghua 4
#6 Li Dawei 3
#7 Jin Song 3
#8 Xu Jing 3
#9 Wang Hongyu 3
#10 Sun Tieli 3

Latest patents

Publication Filing date Title
CN107038265A Computing architecture including FPGA circuitry and use its EDA design methods
CN107038267A A kind of design method of fpga chip elementary cell
CN107037870A A kind of FPGA power control circuits and fpga chip
CN107015880A A kind of FPGA circuitry and its configuration file processing method
CN106936437A Digital analog converter, the analog-digital converter including it and realization method of layout
CN106934079A A kind of carry chain process mapping method based on fpga chip
CN106934077A A kind of Time Series Analysis Method of accurate block carry chain
CN106934080A A kind of high-performance clock signal drives the layout method of register
CN106033642A Monitoring and control terminal and system
CN105991016A Power change-over switch device of chip internal special module and chip
CN105990823A Electrostatic discharge (ESD) protection structure at chip input/output port and chip
CN105989197A Clock tree routing method based on SAT algorithm
CN105808471A FPGA (Field Programmable Gate Array) chip time delay information storage method and device, and FPGA chip time delay information access method and device
CN105812841A CVBS signal compression/decompression method, CVBS signal transmitting/receiving device and CVBS signal transmitting/receiving system
CN105811971A Counter-based variable frequency clock source and FPGA device
CN105808795A FPGA chip global placement optimization method based on temporal constraint
CN105680848A Method for optimizing FPGA (Field-Programmable Gate Array) chip layout based on area clock
CN105653748A Clock tree resource allocation method and clock tree configuration
CN105630529A Loading method of FPGA (Field Programmable Gate Array) configuration file, and decoder
CN105574053A Compression method and apparatus for FPGA configuration file