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Transmitting line based on DDR write access
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High-speed data synchronous circuit and method of data synchronization
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The method realized the digital circuit of clock cycle and realize a quarter clock cycle
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The transmitting line of random code jittering noise is eliminated in a kind of mipi
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A method of realizing that the order of a variety of DDR agreements is sent
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A kind of DLL element circuit based on ONFI
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A kind of level shifting circuit
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A kind of ONFI interface write access transmitting line of multi-mode
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A kind of LVDS interface circuit
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A kind of ONFI drill circuit of multi-mode
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A kind of LVDS transmitting line
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A kind of ONFI interface transmitting line of multi-mode
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DDR receiver reference level circuits
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A kind of ddr interface for flip-chip packaged
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The method of ddr interface circuit adjust automatically reference level VREF
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Single supply domain turns the implementation method of multi-power domain and ddr interface reference current
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A kind of interface that bonding line encapsulation is shared with flip-chip packaged
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A kind of ddr interface circuit of adjust automatically signal dutyfactor
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High-efficiency charge pump
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Low-power-dissipation low-dropout voltage regulator
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