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TILERA CORP

Overview
  • Total Patents
    32
  • GoodIP Patent Rank
    234,494
About

TILERA CORP has a total of 32 patent applications. Its first patent ever was published in 2005. It filed its patents most often in United States, China and EPO (European Patent Office). Its main competitors in its focus markets computer technology, digital networks and environmental technology are HENRY G GLENN, FXI TECHNOLOGIES AS and DAY BRIAN A.

Patent filings in countries

World map showing TILERA CORPs patent filings in countries
# Country Total Patents
#1 United States 29
#2 China 1
#3 EPO (European Patent Office) 1
#4 WIPO (World Intellectual Property Organization) 1

Patent filings per year

Chart showing TILERA CORPs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Agarwal Anant 17
#2 Wentzlaff David 16
#3 Mattina Matthew 10
#4 Ramey Carl 4
#5 Ramey Carl G 4
#6 Bratt Ian R 4
#7 Bratt Ian Rudolf 3
#8 Steele Kenneth M 2
#9 Bao Liewei 2
#10 Metcalf Christopher D 1

Latest patents

Publication Filing date Title
US10210092B1 Managing cache access and streaming data
US2014122560A1 High performance, scalable multi chip interconnect
US8045546B1 Configuring routing in mesh networks
US8050256B1 Configuring routing in mesh networks
US2009077437A1 Method and system for routing scan chains in an array of processor resources
US7853755B1 Caching in multicore and multiprocessor architectures
US7877401B1 Pattern matching
US2008288683A1 Method and system for managing a plurality of I/O interfaces with an array of multicore processor resources in a semiconductor chip
US7805392B1 Pattern matching in a multiprocessor environment with finite state automaton transitions based on an order of vectors in a state transition table
US7793074B1 Directing data in a parallel processing environment
US7882307B1 Managing cache memory in a parallel processing environment
US7539845B1 Coupling integrated circuits in a parallel processing environment
US7461210B1 Managing set associative cache memory according to entry type
US7805577B1 Managing memory access in a parallel processing environment
US7636835B1 Coupling data in a parallel processing environment
US7624248B1 Managing memory in a parallel processing environment
US7774579B1 Protection in a parallel processing environment using access information associated with each switch to prevent data from being forwarded outside a plurality of tiles
US7620791B1 Mapping memory in a parallel processing environment
US7577820B1 Managing data in a parallel processing environment
US7668979B1 Buffering data in a parallel processing environment