Conditional load instructions in an out-of-order execution microprocessor
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Conditional store instructions in an out-of-order execution microprocessor
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Microprocessor that translates conditional load/store instructions into variable number of microinstructions
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Generating constant for microinstructions from modified immediate field during instruction translation
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Conditional non-branch instruction prediction
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Heterogeneous ISA microprocessor with shared hardware ISA registers
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Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA)
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Load multiple and store multiple instructions in a microprocessor that emulates banked registers
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Multi-core microprocessor that performs x86 ISA and ARM ISA machine language program instructions by hardware translation into microinstructions executed by common execution pipeline
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Heterogeneous ISA microprocessor that preserves non-ISA-specific configuration state when reset to different ISA
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Emulation of execution mode banked registers
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Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor
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Efficient conditional ALU instruction in read-port limited register file microprocessor
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Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor
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Distributed management of a shared power source to a multi-core microprocessor
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Multi-core processor with core selectively disabled by kill instruction of system software and resettable only via external pin
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Power state synchronization in a multi-core processor
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Master core discovering enabled cores in microprocessor comprising plural multi-core dies
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Decentralized power management distributed among multiple processor cores
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Tracer configuration and enablement by reset microcode