Decoding method for complementary code keying (CCK) signals with correlation of reception frequency in butterfly appliance in first step, and determination of transmitted sequence in next step for determining smaller Euclidean distance
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Method and arrangement for the efficient control of processors
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Method for the controlled shutdown of data processing units
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Burst access method on co-processors
DE10206830A1
Method and arrangement for merging data from parallel data paths
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Method for providing a design, test and development environment and a system for executing the method
DE10204345A1
Command processing procedures
DE10204344A1
Method for realizing data multi-path configuration for data communication between data process units of ICU, uses command word for ICU as coded command word made available processor system
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Method for generating instruction words for controlling functional units
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Procedure for determining a maximum or minimum
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Arrangement for addressing memory in a parallel-processing strip designed processor, such as a SIMD or super-scalar processor, whereby a local address generation unit is used in addition to an address generation unit
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Method for decoding spread-spectrum coded signals e.g. for communications technology, requires addition of first product from real-input signal and second product from imaginary-part input signal to real-part output signal
DE10155486A1
Arrangement for processing status information from external units
AU1813802A
Method for generating soft bit information from gray coded signals
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Method and arrangement for communication in a wireless communication network
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Procedure for polynomial calculation with 1-bit coefficients
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Method and arrangement for implementing scrambler algorithms in processor-implemented data paths
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Method and device for executing scrambler mechanisms
DE10136577A1
Method for minimizing power use during execution of program code in a portable computer, mobile phone, etc. wherein code is stored in a register during coding so that no-operation commands in particular are not executed
DE10128339A1
Development of the circuit arrangements used in digital signal processing technology especially using the HDL development language to generate a development circuit arrangement for comparison with a reference model
