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SYNOPSYS INC

Overview
  • Total Patents
    2,490
  • GoodIP Patent Rank
    1,644
  • Filing trend
    ⇩ 45.0%
About

SYNOPSYS INC has a total of 2,490 patent applications. It decreased the IP activity by 45.0%. Its first patent ever was published in 1991. It filed its patents most often in United States, China and WIPO (World Intellectual Property Organization). Its main competitors in its focus markets computer technology, semiconductors and optics are GRADIENT DESIGN AUTOMATION INC, JONES ANDREW MICHAEL and HUSH TECHNOLOGIES INVEST LTD.

Patent filings per year

Chart showing SYNOPSYS INCs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Moroz Victor 246
#2 Kawa Jamil 119
#3 Mcelvain Kenneth S 71
#4 Lin Xi-Wei 48
#5 Pramanik Dipankar 48
#6 Pierrat Christophe 48
#7 Melvin Iii Lawrence S 42
#8 Kapur Rohit 39
#9 Chiang Charles C 37
#10 Larzul Ludovic Marc 30

Latest patents

Publication Filing date Title
WO2021076622A1 Predicting defect rate based on lithographic model parameters
US2021110093A1 State table complexity reduction in a hierarchical verification flow
US2021088913A1 Lithography improvement based on defect probability distributions and critical dimension variations
WO2021062040A1 Lithography improvement based on defect probability distributions and critical dimension variations
US2021089699A1 Seamless transition between routing modes
US2021090639A1 Enhanced read sensing margin for sram cell arrays
US2021089695A1 Logic simulation of circuit designs using on-the-fly bit reduction for constraint solving
WO2021050434A1 Machine-learning driven prediction in integrated circuit design
US2021064790A1 Scalable formal security verification of circuit designs
US2021064977A1 Neural network based mask synthesis for integrated circuits
US2021117601A1 Machine-learning enhanced compiler
WO2021030468A1 Methods and systems to perform automated routing
US2021042459A1 Automatic derivation of integrated circuit cell mapping rules in an engineering change order flow
WO2021034495A1 Applying reticle enhancement technique recipes based on failure modes predicted by an artificial neural network
US2021034804A1 Refining multi-bit flip flops mapping without explicit de-banking and re-banking
US2021018831A1 Enforcing mask synthesis consistency across random areas of integrated circuit chips
US2021019461A1 Register transfer level (rtl) image recognition
WO2020264330A1 Waveform consruction using interploation of data points
US2020401750A1 Verifying glitches in reset path using formal verification and simulation
US2020401749A1 Hierarchical abstraction flow using parameter inference