US2007168899A1
|
|
Design method and architecture for power gate switch placement and interconnection using tapless libraries
|
TW200620486A
|
|
Design method and architecture for power gate switch placement
|
US2007024318A1
|
|
Automatic extension of clock gating technique to fine-grained power gating
|
US2006114025A1
|
|
Design method and architecture for power gate switch placement
|
US2005138588A1
|
|
Current scheduling system and method for optimizing multi-threshold CMOS designs
|
US6807660B1
|
|
Vectorless instantaneous current estimation
|
US6698006B1
|
|
Method for balanced-delay clock tree insertion
|
US6701506B1
|
|
Method for match delay buffer insertion
|
US6701507B1
|
|
Method for determining a zero-skew buffer insertion point
|
US6754877B1
|
|
Method for optimal driver selection
|
US6701505B1
|
|
Circuit optimization for minimum path timing violations
|
US6598209B1
|
|
RTL power analysis using gate-level cell power models
|
US6591407B1
|
|
Method and apparatus for interconnect-driven optimization of integrated circuit design
|
US6311312B1
|
|
Method for modeling a conductive semiconductor substrate
|
US6574787B1
|
|
Method and apparatus for logic synthesis (word oriented netlist)
|
US6519755B1
|
|
Method and apparatus for logic synthesis with elaboration
|
US6493648B1
|
|
Method and apparatus for logic synthesis (inferring complex components)
|
US6381730B1
|
|
Method and system for extraction of parasitic interconnect impedance including inductance
|