| # | Country | Total Patents | |
|---|---|---|---|
| #1 | France | 4 | |
| #2 | China | 3 | |
| #3 | EPO (European Patent Office) | 3 | |
| #4 | Republic of Korea | 3 | |
| #5 | Brazil | 2 | |
| #6 | United States | 2 | |
| #7 | Russian Federation | 1 | |
| #8 | Singapore | 1 | |
| #9 | Taiwan | 1 | |
| #10 | WIPO (World Intellectual Property Organization) | 1 |
| # | Industry | |
|---|---|---|
| #1 | Computer technology | |
| #2 | Measurement | |
| #3 | Telecommunications | |
| #4 | Semiconductors | |
| #5 | Digital networks |
| # | Name | Total Patents |
|---|---|---|
| #1 | Lambert Cyrille | 7 |
| #2 | Palmade Romain Pierre | 7 |
| #3 | Croguennec Alexandre | 7 |
| #4 | Fusella Yves | 4 |
| #5 | Bayon Sebastien | 4 |
| #6 | Charbouillot Samuel | 4 |
| #7 | Ricard Stephane | 4 |
| #8 | Bayon Sébastien | 3 |
| #9 | Yves Fusella | 2 |
| #10 | Rikar Stefan | 1 |
| Publication | Filing date | Title |
|---|---|---|
| US2016217363A1 | Microelectronic chip with multiple contacts | |
| FR3035987A1 | Method for manufacturing a chip card by printing a conductive ink | |
| FR3033412A1 | INTEGRATED CIRCUIT TESTER ON A SILICON GALETTE AND INTEGRATED CIRCUIT. | |
| FR2977047A1 | Method for managing endurance of nonvolatile memories |