US2013326160A1
|
|
Gather using index array and finite state machine
|
US2013262926A1
|
|
Recoverable parity and residue error
|
US2012166509A1
|
|
Performing reciprocal instructions with high accuracy
|
US2009327665A1
|
|
Efficient parallel floating point exception handling in a processor
|
US2009327661A1
|
|
Mechanisms to handle free physical register identifiers for smt out-of-order processors
|
US2009327657A1
|
|
GENERATING AND PERFORMING DEPENDENCY CONTROLLED FLOW COMPRISING MULTIPLE MICRO-OPERATIONS (uops)
|
US2009172358A1
|
|
Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits
|
US2007005940A1
|
|
System, apparatus and method of executing a micro operation
|