TW200928956A
|
|
Method and system for supporting multiple display devices
|
US7079133B2
|
|
Superscalar 3D graphics engine
|
US7259765B2
|
|
Head/data scheduling in 3D graphics
|
CN1504854A
|
|
Method and system for reading data from a memory
|
US7159003B1
|
|
Method and apparatus for generating sign-digit format of sum of two numbers
|
US7146486B1
|
|
SIMD processor with scalar arithmetic logic units
|
US6989837B2
|
|
System and method for processing memory with YCbCr 4:2:0 planar video data format
|
US7154487B2
|
|
Power saving palette look-up table for graphics controller
|
US6775417B2
|
|
Fixed-rate block-based image compression with inferred pixel values
|
US7471298B1
|
|
Fetching pixel data with reduced memory bandwidth requirement
|
US6707460B1
|
|
Fast and cheap correct resolution conversion for digital numbers
|
US7119809B1
|
|
Parallel architecture for graphics primitive decomposition
|
US6766281B1
|
|
Matched texture filter design for rendering multi-rate data samples
|
US6828983B1
|
|
Selective super-sampling/adaptive anti-aliasing of complex 3D data
|
US6972760B2
|
|
Area and span based Z-buffer
|
US6611265B1
|
|
Multi-stage fixed cycle pipe-lined lighting equation evaluator
|
US6791544B1
|
|
Shadow rendering system and method
|
US6590579B1
|
|
System for low miss rate replacement of texture cache lines
|
US6614442B1
|
|
Macroblock tiling format for motion compensation
|
US6625665B1
|
|
Command interpretation system and method
|