Early retirement of store operation past exception reporting pipeline stage in strongly ordered processor with load/store queue entry retained until completion
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Resonance limiter circuits for an integrated circuit
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Prefetch unit
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Digital jitter detector
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Wearout compensation mechanism using back bias technique
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Pulsed flop with scan circuitry
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Combined multiplex or/flop
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Pulsed flop with embedded logic
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Retry mechanism in cache coherent communication among agents
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Digital leakage detector that detects transistor leakage current in an integrated circuit
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Ordering rule and fairness implementation
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Unified DMA
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Voltage-controlled oscillator for low-voltage, wide frequency range operation
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Combined buffer for snoop, store merging, load miss, and writeback operations
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Partially decoded register renamer
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Channelized flow control
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Explicit flow control in Gigabit/10 Gigabit Ethernet system
