US2017364408A1
|
|
Multiple read and write port memory
|
WO2017199186A1
|
|
Egress flow mirroring in a network device
|
US9824744B1
|
|
High-speed differential interface circuit with fast setup time
|
US9805822B1
|
|
Built-in self-test for adaptive delay-locked loop
|
TW201727519A
|
|
Method to produce a semiconductor wafer for versatile products
|
US9705485B1
|
|
High-resolution current and method for generating a current
|
US9755881B1
|
|
Receiver with data-aided automatic frequency control
|
KR20160135675A
|
|
Integrated circuit having regulator controlled based on operation speed
|
US2016320989A1
|
|
Multi-bank memory with one read port and one or more write ports per cycle
|
US9864546B1
|
|
FIFO-based operations for redundant array of independent disks (RAID) device
|
US2016162359A1
|
|
System and method for performing simultaneous read and write operations in a memory
|
US2016162426A1
|
|
Optimal sampling of data-bus signals using configurable individual time delays
|
US9672897B1
|
|
Method and apparatus for memory speed characterization
|
US9686209B1
|
|
Method and apparatus for storing packets in a network device
|
US2015212795A1
|
|
Interfacing with a buffer manager via queues
|
US9838341B1
|
|
Methods and apparatus for memory resource management in a network device
|
US2015172198A1
|
|
Methods and network device for oversubscription handling
|
US9509285B1
|
|
Power saving latches
|
US9565762B1
|
|
Power delivery network in a printed circuit board structure
|
US9866339B1
|
|
Method and apparatus for securing clock synchronization in a network
|