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JASPER DESIGN AUTOMATION INC

Overview
  • Total Patents
    20
  • GoodIP Patent Rank
    238,374
About

JASPER DESIGN AUTOMATION INC has a total of 20 patent applications. Its first patent ever was published in 2000. It filed its patents most often in United States and WIPO (World Intellectual Property Organization). Its main competitors in its focus markets computer technology are BEIJING SAFE CODE TECHNOLOGY CO LTD, Hefei lianbao information technology co ltd and KUSHLER CLIFFORD A.

Patent filings in countries

World map showing JASPER DESIGN AUTOMATION INCs patent filings in countries

Patent filings per year

Chart showing JASPER DESIGN AUTOMATION INCs patent filings per year from 1900 to 2020

Focus industries

# Industry
#1 Computer technology

Focus technologies

Top inventors

# Name Total Patents
#1 Singhal Vigyan 7
#2 Ip Chung-Wah Norris 7
#3 Loh Lawrence 6
#4 Wong-Toi Howard 5
#5 Higgins Joseph E 4
#6 Ip Chung-Wah N 3
#7 Lin Chien-Liang 3
#8 Caldeira Jr Antonio Celso 2
#9 Mazzawi Jamil R 2
#10 Coelho Jr Claudionor José Nunes 2

Latest patents

Publication Filing date Title
US9460252B1 Functional property ranking
US9158874B1 Formal verification coverage metrics of covered events for circuit design properties
WO2015062013A1 Data propagation analysis for debugging a circuit design
US2015100932A1 Manipulation of traces for debugging a circuit design
US8984461B1 Visualization constraints for circuit designs
US8954904B1 Veryifing low power functionality through RTL transformation
US9104824B1 Power aware retention flop list analysis and modification
US9449196B1 Security data path verification
US8826201B1 Formal verification coverage metrics for circuit design properties
US7506288B1 Interactive analysis and debugging of a circuit design during functional verification of the circuit design
US7895552B1 Extracting, visualizing, and acting on inconsistencies between a circuit design and its abstraction
US7421668B1 Meaningful visualization of properties independent of a circuit design
US7418678B1 Managing formal verification complexity of designs with counters
US7237208B1 Managing formal verification complexity of designs with datapaths
US7065726B1 System and method for guiding and optimizing formal verification for a circuit design
US2004194046A1 Trace based method for design navigation
US2003208730A1 Method for verifying properties of a circuit model
US6611947B1 Method for determining the functional equivalence between two circuit models in a distributed computing environment