US2014033162A1
|
|
Determining optimal gate sizes by using a numerical solver
|
US2013326449A1
|
|
Incremental elmore delay calculation
|
US2013145337A1
|
|
Delta-slack propagation for circuit optimization
|
US2013318488A1
|
|
Excluding library cells for delay optimization in numerical synthesis
|
US2013283222A1
|
|
Numerical delay model for a technology library cell
|
US2013145336A1
|
|
Progressive circuit evaluation for circuit optimization
|
US2011289464A1
|
|
Global timing modeling within a local context
|
US2011191732A1
|
|
Method and apparatus for determining a robustness metric for a circuit design
|
US2011185333A1
|
|
Global leakage power optimization
|
US2011185334A1
|
|
Zone-based leakage power optimization
|