US2008259798A1
|
|
Flow and congestion control in switch architectures for multi-hop, memory efficient fabrics
|
US2008181103A1
|
|
Traffic distribution techniques utilizing initial and scrambled hash values
|
US2006120189A1
|
|
Logic synthesis of multi-level domino asynchronous pipelines
|
US2006155938A1
|
|
Shared-memory switch fabric architecture
|
EP1647030A2
|
|
Asynchronous static random access memory
|
US2004111589A1
|
|
Asynchronous multiple-order issue system architecture
|
US2004151209A1
|
|
Asynchronous system-on-a-chip interconnect
|
US2005013356A1
|
|
Methods and apparatus for providing test access to asynchronous circuits and systems
|
US2004100900A1
|
|
Message transfer system
|
US2004034844A1
|
|
Methods and apparatus for facilitating physical synthesis of an integrated circuit design
|
US2003165158A1
|
|
Techniques for facilitating conversion between asynchronous and synchronous domains
|
US2003146073A1
|
|
Asynchronous crossbar with deterministic or arbitrated control
|