|
US2012204008A1
|
|
Processor with a Hybrid Instruction Queue with Instruction Elaboration Between Sections
|
|
US2012204005A1
|
|
Processor with a coprocessor having early access to not-yet issued instructions
|
|
US2012204004A1
|
|
Hybrid queue for storing instructions from fetch queue directly in out-of-order queue or temporarily in in-order queue until space is available
|
|
US2013173886A1
|
|
Processor with Hazard Tracking Employing Register Range Compares
|
|
US2012110037A1
|
|
Methods and Apparatus for a Read, Merge and Write Register File
|
|
US2007260662A1
|
|
Controlled-precision iterative arithmetic logic unit
|
|
US2007203967A1
|
|
Floating-point processor with reduced power requirements for selectable subprecision
|
|
US2007174379A1
|
|
Pre-saturating fixed-point multiplier
|
