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BIRAN GIORA

Overview
  • Total Patents
    21
About

BIRAN GIORA has a total of 21 patent applications. Its first patent ever was published in 2005. It filed its patents most often in United States. Its main competitors in its focus markets computer technology, digital networks and basic communication technologies are TOFANO JEFFREY VINCENT, UNIV PEKING SZ GRADUATE SCHOOL and CRADLE TECHNOLOGIES.

Patent filings in countries

World map showing BIRAN GIORAs patent filings in countries
# Country Total Patents
#1 United States 21

Patent filings per year

Chart showing BIRAN GIORAs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Biran Giora 21
#2 Van Lunteren Jan 10
#3 Hagleitner Christoph 10
#4 Heil Timothy H 8
#5 Makhervaks Vadim 5
#6 Hoover Russell D 4
#7 Shalev Leah 4
#8 Granovsky Ilya 3
#9 Golander Amit 3
#10 Heil Timothy Hume 2

Latest patents

Publication Filing date Title
US8593308B1 Method of accelerating dynamic huffman decompaction within the inflate algorithm
US2013159811A1 Method of hybrid compression acceleration utilizing special and general purpose processors
US2012284446A1 Accelerator engine emulation over an interconnect link
US2012254587A1 Methods for the transmission of accelerator commands and corresponding command structure to remote hardware accelerator engines over an interconnect link
US2012203761A1 Pattern matching accelerator
US2012203755A1 Multiple rule bank access scheme for use in a pattern matching accelerator
US2012203718A1 Algorithm engine for use in a pattern matching accelerator
US2012203754A1 Performance monitoring mechanism for use in a pattern matching accelerator
US2012203730A1 Pattern matching engine for use in a pattern matching accelerator
US2012203756A1 Local results processor for use in a pattern matching accelerator
US2012203970A1 Software and hardware managed dual rule bank cache for use in a pattern matching accelerator
US2012203753A1 Upload manager for use in a pattern matching accelerator
US2012204000A1 Address translation for use in a pattern matching accelerator
US2012203729A1 Multiple hash scheme for use in a pattern matching accelerator
US2011071990A1 Fast history based compression in a pipelined architecture
US2009271802A1 Application and verb resource management
US2009006932A1 Device, system and method of modification of PCI express packet digest
US2007136554A1 Memory operations in a virtualized system
US2006095567A1 Method of offloading iSCSI PDU corruption-detection digest generation from a host processing unit, and related iSCSI offload engine