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ARIMILLI LAKSHMINARAYANA B

Overview
  • Total Patents
    31
About

ARIMILLI LAKSHMINARAYANA B has a total of 31 patent applications. Its first patent ever was published in 2007. It filed its patents most often in United States. Its main competitors in its focus markets computer technology, digital networks and machines are PREVX LTD, NAMU TECH CO LTD and NET THUNDER LLC.

Patent filings in countries

World map showing ARIMILLI LAKSHMINARAYANA Bs patent filings in countries
# Country Total Patents
#1 United States 31

Patent filings per year

Chart showing ARIMILLI LAKSHMINARAYANA Bs patent filings per year from 1900 to 2020

Focus industries

Top inventors

# Name Total Patents
#1 Arimilli Lakshminarayana B 31
#2 Arimilli Ravi K 23
#3 Rajamony Ramakrishnan 16
#4 Speight William E 9
#5 Xue Hanhong 7
#6 Blackmore Robert S 7
#7 Starke William J 7
#8 Guthrie Guy L 6
#9 Lewis Jerry D 4
#10 Drerup Bernard C 4

Latest patents

Publication Filing date Title
US2011238956A1 Collective acceleration unit tree structure
US2011173258A1 Collective acceleration unit tree flow control and retransmit
US2010269027A1 User level message broadcast mechanism in distributed computing environment
US2010070710A1 Techniques for cache injection in a processor system
US2009199182A1 Notification by task of completion of GSM operations at target node
US2009198956A1 System and Method for Data Processing Using a Low-Cost Two-Tier Full-Graph Interconnect Architecture
US2009198918A1 Host fabric interface (HFI) to perform global shared memory (GSM) operations
US2009198916A1 Method and Apparatus for Supporting Low-Overhead Memory Locks Within a Multiprocessor System
US2009198920A1 Processing Units Within a Multiprocessor System Adapted to Support Memory Locks
US2009198695A1 Method and Apparatus for Supporting Distributed Computing Within a Multiprocessor System
US2009198933A1 Method and apparatus for handling multiple memory requests within a multiprocessor system
US2009198971A1 Binding a process to a special purpose processing element having characteristics of a processor
US2009198912A1 Cache management for partial cache line operations
US2009198849A1 Memory lock mechanism for a multiprocessor system
US2009198914A1 Interconnect operation indicating acceptability of partial data delivery
US2009199195A1 Generating and issuing global shared memory operations via a send FIFO
US2009199191A1 Notification to task of completion of GSM operations by initiator node
US2009199209A1 Guaranteeing delivery of multi-packet GSM messages
US2009199194A1 Mechanism to prevent illegal access to task address space by unauthorized tasks
US2009198957A1 Performing dynamic request routing based on broadcast queue depths