|
US2013170272A1
|
|
Optimized threshold search in analog memory cells
|
|
US2013117606A1
|
|
Data protection from write failures in nonvolatile memory
|
|
US2014026010A1
|
|
Parallel chien search over multiple code words
|
|
US2013073928A1
|
|
Power-optimized decoding of linear codes
|
|
US2012221913A1
|
|
Error correction codes for incremental redundancy
|
|
US8495465B1
|
|
Error correction coding over multiple memory pages
|
|
US8601352B1
|
|
Efficient LDPC codes
|
|
US2010332955A1
|
|
Chien search using multiple basis representation
|
|
US8429498B1
|
|
Dual ECC decoder
|
|
US8484541B1
|
|
Configurable encoder for cyclic error correction codes
|
|
US8327242B1
|
|
High-performance ECC decoder
|
|
US2009187803A1
|
|
Decoding of error correction code using partial bit inversion
|
|
US2009106485A1
|
|
Reading analog memory cells using built-in multi-threshold commands
|
