|
US2013249612A1
|
|
Method and apparatus for source-synchronous signaling
|
|
US2014035650A1
|
|
Low-latency, frequency-agile clock multiplier
|
|
US2014043105A1
|
|
Integrated circuit having a multiplying injection-locked oscillator
|
|
US2013159657A1
|
|
Memory controller with fast reacquisition of read timing to support rank switching
|
|
US2013044845A1
|
|
Low power edge and data sampling
|
|
US2011208990A1
|
|
Regulation of memory IO timing using programmatic control over memory device IO timing
|
|
US2009279637A1
|
|
Bit-error rate in fixed line-rate systems
|
|
US2011033007A1
|
|
Multi-band, multi-drop chip to chip signaling
|
|
US2005259692A1
|
|
Crosstalk minimization in serial link systems
|
|
US8861667B1
|
|
Clock data recovery circuit with equalizer clock calibration
|
