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VIA CYRIX INC

Overview
  • Total Patents
    44
About

VIA CYRIX INC has a total of 44 patent applications. Its first patent ever was published in 1993. It filed its patents most often in United States, Taiwan and EPO (European Patent Office). Its main competitors in its focus markets computer technology, environmental technology and basic communication technologies are ANDES TECHNOLOGY CORP, POTASH HANAN and PLONDKE ERICH JAMES.

Patent filings in countries

World map showing VIA CYRIX INCs patent filings in countries
# Country Total Patents
#1 United States 34
#2 Taiwan 5
#3 EPO (European Patent Office) 3
#4 China 2

Patent filings per year

Chart showing VIA CYRIX INCs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Shelor Charles F 11
#2 Miller William V 6
#3 Green Daniel W 5
#4 Hervin Mark W 4
#5 Bluhm Mark 3
#6 Brightman Thomas B 3
#7 Duncan Richard L 2
#8 Funk Andrew D 2
#9 Mcmahan Steven C 2
#10 Garibay Jr Raul A 2

Latest patents

Publication Filing date Title
US6983359B2 Processor and method for pre-fetching out-of-order instructions
TWI220472B Low-power cache and method for operating same
US2004268089A1 Apparatus and method for accessing registers in a processor
US2004268103A1 Apparatus and method for managing a processor pipeline in response to exceptions
US6844767B2 Hierarchical clock gating circuit and method
US2004255103A1 Method and system for terminating unnecessary processing of a conditional instruction in a processor
US2004243764A1 Tag array access reduction in a cache memory
US2004230781A1 Method and system for predicting the execution of conditional instructions in a processor
US2004225839A1 Method and system for cache power reduction
US7194601B2 Low-power decode circuitry and method for a processor having multiple decoders
US7594103B1 Microprocessor and method of processing instructions for responding to interrupt condition
US2004098564A1 Status register update logic optimization
US2003227300A1 Multiple asynchronous switching system
US6412063B1 Multiple-operand instruction in a two operand pipeline and processor employing the same
US6275926B1 System and method for writing back multiple results over a single-result bus and processor employing the same
US6351797B1 Translation look-aside buffer for storing region configuration bits and method of operation
US6009533A Speculative bus cycle acknowledge for 1/2X core/bus clocking
US6351789B1 Built-in self-test circuit and method for validating an associative data array
US6005425A PLL using pulse width detection for frequency and phase error correction
US6301647B1 Real mode translation look-aside buffer and method of operation