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US6319762B1
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Method for fabricating poly-spacers
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US6342422B1
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Method for forming MOSFET with an elevated source/drain
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US6365504B1
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Self aligned dual damascene method
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US6303417B1
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Method of forming self-aligned planarization twin-well by using fewer mask counts for CMOS transistors
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TW402813B
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The structure of high-density buried bit line flash EEPROM memory and its formation method
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US6281542B1
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Flower-like capacitor structure for a memory cell
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TW392341B
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Method for forming multi-fin and multi-cylinder capacitor of high density DRAM
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TW396621B
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Structure and process for high density multi-state mask read only memory with double poly-gate
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TW392347B
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High-density buried bit line flash EEPROM memory structure and method for manufacturing the same
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TW396552B
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High density trench type contact-free nonvolatile memory
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TW396419B
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A method of manufacturing resistors with high ESD resistance and salicide CMOS transistor
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TW392291B
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Method of forming shallow trench isolation
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TW389996B
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Method for forming vertically modulated well of CMOS without photoresist outgassing in high energy ion implantation
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TW398074B
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Mask ROM with low mask number and its manufacturing
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TW379445B
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Method of manufacturing capacitors for DRAMs
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TW400584B
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Method of forming the ultra-short channel and MOSFETs with raised S/D on the ultra-thin SOI substrate
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TW390010B
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Method for removing buried contact trench
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TW396417B
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Method for the formation of a deep-submicron CMOS with self-aligneded silicide contact and extended source/drain contact
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TW384549B
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Method of forming metal oxide semiconductor field effect transistor having recessed self-alignment silicide metal and slowly tapered S/D junctions
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TW383470B
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Method of forming CMOS transistor employing self-aligned flat twin-well
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