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Multi-rail asynchronous flow with completion detection and system and method for designing the same
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FIFO using asynchronous logic to interface between clocked logic circuits
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Semi-dynamic and dynamic threshold gates with modified pull-up structures
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Asynchronous registers with embedded acknowledge collection
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Programmable gate array
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Dynamic threshold gates with embedded registration
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Autonomously cycling data processing architecture
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Null convention threshold gate
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Null convention interface circuits
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Null convention register file
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