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SYNTHESYS RES INC

Overview
  • Total Patents
    53
About

SYNTHESYS RES INC has a total of 53 patent applications. Its first patent ever was published in 2001. It filed its patents most often in Japan, EPO (European Patent Office) and United States. Its main competitors in its focus markets digital networks, measurement and basic communication technologies are NAGOYA MITSUGU, NINGBO SANXING MEDICAL AND ELECTRIC CO LTD and ANHUI UDAN TECH CO LTD.

Patent filings in countries

World map showing SYNTHESYS RES INCs patent filings in countries
# Country Total Patents
#1 Japan 16
#2 EPO (European Patent Office) 15
#3 United States 12
#4 Canada 10

Patent filings per year

Chart showing SYNTHESYS RES INCs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Poskatcheev Andrei 17
#2 Waschura Thomas E 17
#3 Willis Andre 9
#4 Waschura Thomas Eugene 9
#5 Fincher Clint 9
#6 Willis Andrei 7
#7 Thandapani Senthil 5
#8 Waschura James R 3
#9 Bertrand Keith 3
#10 Waschura James E 3

Latest patents

Publication Filing date Title
US2007296476A1 Synchronizing clock and aligning signals for testing electronic devices
US2006210005A1 Method and apparatus for detecting linear phase error
EP1701443A1 Voltage controlled oscillator with additional phase control
JP2006254447A Method and device for modulating phase of edge-detecting signal
JP2006254440A Method and device for detecting linear-phase error
JP2006250934A Method and device for measuring duty cycle
CA2538485A1 Method and apparatus for detecting linear phase error
US2006069971A1 Method and apparatus for deferred decision signal quality analysis
JP2007005842A Method and device for measuring and displaying data dependent eye diagram
EP1560333A2 A method and apparatus for generating variable delay
US2005246601A1 Method and apparatus to measure and display data dependent eye diagrams
US2005222798A1 Method and apparatus for creating performance limits from parametric measurements
US7477078B2 Variable phase bit sampling with minimized synchronization loss
US2007033448A1 Method and apparatus for using dual bit decisions to measure bit errors and event occurrences
JP2004289387A Method and system for forming eye diagram using binary data bit decision device
EP1460793A1 A method and apparatus for counting the errors of a data signal that are outside the limits of an eye mask
EP1460792A1 Method and system for creating an eye diagram
EP1315327A2 Apparatus and method for sampling eye diagrams with window comparators
US7062733B1 Method and apparatus for delay line calibration
US2003177438A1 Method and system for creating an eye diagram using a binary data bit decision mechanism