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Picoengine pool transactional memory architecture
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Hardware prefix reduction circuit
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Inter-packet interval prediction operating algorithm
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Transactional memory that performs a TCAM 32-bit lookup operation
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Inter-packet interval prediction learning algorithm
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Transactional memory that performs a split 32-bit lookup operation
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Transactional memory that performs an ALUT 32-bit lookup operation
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Network appliance that determines what processor to send a future packet to based on a predicted future arrival time
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Transactional memory that performs an atomic look-up, add and lock operation
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Transactional memory that performs a CAMR 32-bit lookup operation
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Transactional memory that performs an atomic metering command
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Transactional memory that performs a direct 32-bit lookup operation
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Transactional memory that performs a direct 24-BIT lookup operation
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Recursive use of multiple hardware lookup structures in a transactional memory
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Transactional Memory that Performs a Statistics Add-and-Update Operation
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Recursive lookup with a hardware trie structure that has no sequential logic elements
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Global event chain in an island-based network flow processor
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Commonality of memory island interface and structure
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Distributed credit FIFO link of a configurable mesh data bus
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