SILICON PERSPECTIVE CORP has a total of 31 patent applications. Its first patent ever was published in 1998. It filed its patents most often in WIPO (World Intellectual Property Organization), Australia and United States. Its main competitors in its focus markets computer technology are STALL JONATHON MICHAEL, LLC PEERF and FUKUYAMA AKIHIKO.
# | Country | Total Patents | |
---|---|---|---|
#1 | WIPO (World Intellectual Property Organization) | 13 | |
#2 | Australia | 9 | |
#3 | United States | 5 | |
#4 | Taiwan | 3 | |
#5 | EPO (European Patent Office) | 1 |
# | Industry | |
---|---|---|
#1 | Computer technology |
# | Technology | |
---|---|---|
#1 | Electric digital data processing |
# | Name | Total Patents |
---|---|---|
#1 | Dai Wei-Jin | 16 |
#2 | Teng Chin-Chi | 10 |
#3 | Igusa Mitsuru | 8 |
#4 | Kao Wei-Lun | 8 |
#5 | Chen Hsi-Chuan | 6 |
#6 | Cheong Kit-Lam | 5 |
#7 | Shen Jia-Jye | 4 |
#8 | Chang Jui-Ming | 4 |
#9 | Chao Ping | 4 |
#10 | Harn Ywh-Pyng | 4 |
Publication | Filing date | Title |
---|---|---|
AU2003208923A1 | Method of estimating path delays in an ic | |
AU2003210734A1 | Ic layout system employing a hierarchical database | |
WO03052644A1 | Gated clock tree synthesis | |
US6578183B2 | Method for generating a partitioned IC layout | |
US6519749B1 | Integrated circuit partitioning placement and routing system | |
US6351840B1 | Method for balancing a clock tree | |
US6256768B1 | Amoeba display for hierarchical layout | |
US6249902B1 | Design hierarchy-based placement |