|
US6519688B1
|
|
Read data valid loop-back for high speed synchronized DRAM controller
|
|
AU4045500A
|
|
Differential charge pump with common mode feedback
|
|
WO0010092A1
|
|
Communicating the status of a peripheral device controller to a host processor
|
|
US6265899B1
|
|
Single rail domino logic for four-phase clocking scheme
|
|
US6393600B1
|
|
Skew-independent memory architecture
|
|
US6093029A
|
|
Vertically stackable integrated circuit
|
|
US6112262A
|
|
System and method for efficiently transferring information between processors
|
|
US6034733A
|
|
Timing and control for deinterlacing and enhancement of non-deterministically arriving interlaced video data
|
|
US6128026A
|
|
Double buffered graphics and video accelerator having a write blocking memory interface and method of doing the same
|
|
WO9900752A1
|
|
Method and apparatus for incorporating dynamic random access memory design modules into an integrated circuit chip design
|
|
US6169418B1
|
|
Efficient routing from multiple sources to embedded DRAM and other large circuit blocks
|
|
US6212490B1
|
|
Hybrid circuit model simulator for accurate timing and noise analysis
|
|
US6076155A
|
|
Shared register architecture for a dual-instruction-set CPU to facilitate data exchange between the instruction sets
|
|
US6075396A
|
|
Using power-on mode to control test mode
|
|
US6389566B1
|
|
Edge-triggered scan flip-flop and one-pass scan synthesis methodology
|
|
US6075398A
|
|
Tunable digital oscillator circuit and method for producing clock signals of different frequencies
|
|
US6041419A
|
|
Programmable delay timing calibrator for high speed data interface
|
|
US6345099B1
|
|
System and method for copy protecting computer graphics
|
|
US6154195A
|
|
System and method for performing dithering with a graphics unit having an oversampling buffer
|
|
AU7389998A
|
|
Software-based dithering method and apparatus using ramp probability logic
|
