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Apparatus and method for dynamically reconfigurable timed flushing of a queue of coalescing write buffers
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Instruction cache address generation technique having reduced delays in fetching missed data
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Facility to allow fast execution of and, or, and test instructions
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Using two barrel shifters to implement shift, rotate, rotate with carry, and shift double as specified by the X86 architecture
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Efficient bit scan mechanism
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Mechanism to simplify built-in self test of a control store unit
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Executing multiple instructions in multi-pipelined processor by dynamically switching memory ports of fewer number than the pipeline
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Branch prediction mechanism
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Execution of data dependent arithmetic instructions in multi-pipeline processors
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Programmable hit and write policy for cache memory test
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