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POLAR SEMICONDUCTOR INC

Overview
  • Total Patents
    18
About

POLAR SEMICONDUCTOR INC has a total of 18 patent applications. Its first patent ever was published in 2002. It filed its patents most often in United States and WIPO (World Intellectual Property Organization). Its main competitors in its focus markets electrical machinery and energy, semiconductors and computer technology are SILERGY SEMICONDUCTOR TECH HANGZHOU CO LTD, SILERGY CORP and SILERGY SEMICONDUCTOR TECH (HANGZHOU) LTD.

Patent filings in countries

World map showing POLAR SEMICONDUCTOR INCs patent filings in countries

Patent filings per year

Chart showing POLAR SEMICONDUCTOR INCs patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Wibben Josh 4
#2 Kosier Steven L 2
#3 Kosier Steven 2
#4 Rho Kyeonglan 2
#5 Fertig Daniel 2
#6 Beckman John C 2
#7 Hoilien Noel 2
#8 Kimber Kurt 2
#9 Metzler Crispin 2
#10 Kimber Kurt N 2

Latest patents

Publication Filing date Title
WO2011140218A2 Multiple output power supply
WO2012128768A1 Series switch bridgeless power supply
US2011115407A1 Simplified control of color temperature for general purpose lighting
US8044699B1 Differential high voltage level shifter
US2010295472A1 Power supply for floating loads
US2011058285A1 Over-current protection device for a switched-mode power supply
US2011037069A1 Method and apparatus for visually determining etch depth
US2010270625A1 Method of fabricating high-voltage metal oxide semiconductor transistor devices
US2009231770A1 Current-mode under voltage lockout circuit
US2008266738A1 Over-current protection device for a switched-mode power supply
US2007290289A1 Diode structure to suppress parasitic current
US2006267146A1 Multilayered emitter window for bipolar junction transistor
US2006270165A1 Multi-layered spacer for lightly-doped drain MOSFETS
US2007120191A1 High trigger current electrostatic discharge protection device
US7071533B1 Bipolar junction transistor antifuse
US7135750B1 Photodiode array having reduced dead space
US7185302B1 Method for generating layouts by chamfering corners of polygons
US7043711B2 System and method for defining semiconductor device layout parameters