Methods and Apparatus for Sharing Nodes in a Network with Connections Based on 1 to K+1 Adjacency Used in an Execution Array Memory Array (XarMa) Processor
US2015039855A1
Methods and apparatus for signal flow graph pipelining that reduce storage of temporary variables
US2011161625A1
Interconnection network connecting operation-configurable nodes according to one or more levels of adjacency in multiple dimensions of communication in a multi-processor and a neural processor
US8103854B1
Methods and apparatus for independent processor node operations in a SIMD array processor
US2006218376A1
Processor composed of memory nodes that execute memory access instructions and cooperate with execution nodes to execute function instructions
US7185177B2
Methods and apparatus for meta-architecture defined programmable instruction fetch functions supporting assembled variable length instruction processors
