|
US2018287611A1
|
|
Low power logic family
|
|
FI20070423A0
|
|
Differential, locally updated Viterbi decoder
|
|
FI20050249A0
|
|
A method for real-time, user-assisted text or symbol recognition and interpretation on mobile devices
|
|
FI20030772A0
|
|
Power rectifier switching, its usage and method in parallel processor network
|
|
FI20020707A0
|
|
Power rectifier connection, its use and method in parallel processor network
|
|
FI20020324A0
|
|
Analog-to-digital converter, power scaler and method to control power scaler function
|
|
FI20010901A0
|
|
Parallel processor networks, processor and method for solving differential equations in a parallel processor network
|
|
FI20002864A0
|
|
Processor, circuit and method for processing images on a parallel processor network
|
|
FI20001221A
|
|
Image processing in a parallel processor network, and the network and cell that is applicable to it
|
