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Netspeed Systems

Overview
  • Total Patents
    73
  • GoodIP Patent Rank
    28,994
  • Filing trend
    ⇧ 100.0%
About

Netspeed Systems has a total of 73 patent applications. It increased the IP activity by 100.0%. Its first patent ever was published in 2012. It filed its patents most often in United States, WIPO (World Intellectual Property Organization) and Republic of Korea. Its main competitors in its focus markets computer technology, digital networks and environmental technology are MARR MICHAEL DAVID, INSPUR BEIJING ELECT INF IND and BLUERISC INC.

Patent filings in countries

World map showing Netspeed Systemss patent filings in countries

Patent filings per year

Chart showing Netspeed Systemss patent filings per year from 1900 to 2020

Top inventors

# Name Total Patents
#1 Kumar Sailesh 73
#2 Norige Eric 42
#3 Philip Joji 17
#4 Rowlands Joe 11
#5 Mitra Sundari 10
#6 Hassan Mahmud 9
#7 Raponi Pier Giorgio 9
#8 Patankar Amit 7
#9 Pusuluri Vishnu Mohan 5
#10 Kongetira Poonacha 5

Latest patents

Publication Filing date Title
US2017063610A1 Hierarchical asymmetric mesh with virtual routers
US2017063626A1 System and method for grouping of network on chip (noc) elements
US2017230253A1 Generating physically aware network-on-chip design from a physical system-on-chip specification
US2017228481A1 Verification low power collateral generation
US2017063609A1 Dynamically configuring store-and-forward channels and cut-through channels in a network-on-chip
US2017060809A1 Automatic generation of physically aware aggregation/distribution networks
US2017063639A1 Generation of network-on-chip layout based on user specified topological constraints
US9568970B1 Hardware and software enabled implementation of power profile management instructions in system on chip
US2017060805A1 Transaction expansion for NoC simulation and NoC design
US9444702B1 System and method for visualization of NoC performance based on simulation output
US2017063734A1 Automatic buffer sizing for optimal network-on-chip design
US9529400B1 Automatic power domain and voltage domain assignment to system-on-chip agents and network-on-chip elements
US9571341B1 Clock gating for system-on-chip elements
US2017060204A1 Automatic generation of power management sequence in a SoC or NoC
US9477280B1 Specification for automatic power management of network-on-chip and system-on-chip
US2017063625A1 Configurable router for a network on chip (NoC)
US2017061041A1 Automatic performance characterization of a network-on-chip (NOC) interconnect
US2015370720A1 Using cuckoo movement for improved cache coherency
US2015358211A1 Transactional traffic specification for network-on-chip design
US2015324288A1 System and method for improving snoop performance