US2017063610A1
|
|
Hierarchical asymmetric mesh with virtual routers
|
US2017063626A1
|
|
System and method for grouping of network on chip (noc) elements
|
US2017230253A1
|
|
Generating physically aware network-on-chip design from a physical system-on-chip specification
|
US2017228481A1
|
|
Verification low power collateral generation
|
US2017063609A1
|
|
Dynamically configuring store-and-forward channels and cut-through channels in a network-on-chip
|
US2017060809A1
|
|
Automatic generation of physically aware aggregation/distribution networks
|
US2017063639A1
|
|
Generation of network-on-chip layout based on user specified topological constraints
|
US9568970B1
|
|
Hardware and software enabled implementation of power profile management instructions in system on chip
|
US2017060805A1
|
|
Transaction expansion for NoC simulation and NoC design
|
US9444702B1
|
|
System and method for visualization of NoC performance based on simulation output
|
US2017063734A1
|
|
Automatic buffer sizing for optimal network-on-chip design
|
US9529400B1
|
|
Automatic power domain and voltage domain assignment to system-on-chip agents and network-on-chip elements
|
US9571341B1
|
|
Clock gating for system-on-chip elements
|
US2017060204A1
|
|
Automatic generation of power management sequence in a SoC or NoC
|
US9477280B1
|
|
Specification for automatic power management of network-on-chip and system-on-chip
|
US2017063625A1
|
|
Configurable router for a network on chip (NoC)
|
US2017061041A1
|
|
Automatic performance characterization of a network-on-chip (NOC) interconnect
|
US2015370720A1
|
|
Using cuckoo movement for improved cache coherency
|
US2015358211A1
|
|
Transactional traffic specification for network-on-chip design
|
US2015324288A1
|
|
System and method for improving snoop performance
|