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MUFF ADAM J

Overview
  • Total Patents
    13
About

MUFF ADAM J has a total of 13 patent applications. Its first patent ever was published in 2007. It filed its patents most often in United States. Its main competitors in its focus markets computer technology and digital networks are WADE GREGORY L, NASUNI CORP and SIMPLIVITY CORP.

Patent filings in countries

World map showing MUFF ADAM Js patent filings in countries
# Country Total Patents
#1 United States 13

Patent filings per year

Chart showing MUFF ADAM Js patent filings per year from 1900 to 2020

Focus industries

Top inventors

# Name Total Patents
#1 Tubbs Matthew R 13
#2 Muff Adam J 13
#3 Shearer Robert A 11
#4 Schardt Paul E 10

Latest patents

Publication Filing date Title
US2013191824A1 Virtualization support for branch prediction logic enable / disable at hypervisor and guest operating system levels
US2013191651A1 Memory address translation-based data encryption with integrated encryption engine
US2013191649A1 Memory address translation-based data encryption/compression
US2013191825A1 System and method for selectively saving and restoring state of branch prediction logic through separate hypervisor-mode and guest-mode and/or user-mode instructions
US2013159668A1 Predecode logic autovectorizing a group of scalar instructions including result summing add instruction to a vector instruction for execution in vector unit with dot product adder
US2013159676A1 Instruction set architecture with extended register addressing using one or more primary opcode bits
US2013159675A1 Instruction predication using unused datapath facilities
US2013159674A1 Instruction predication using instruction filtering
US2013138918A1 Direct interthread communication dataport pack/unpack and load/save
US2013111190A1 Changing opcode of subsequent instruction when same destination address is not used as source address by intervening instructions
US2010191939A1 Trigonometric summation vector execution unit
US2010091787A1 Direct inter-thread communication buffer that supports software controlled arbitrary vector operand selection in a densely threaded network on a chip
US2009158013A1 Method and apparatus implementing a minimal area consumption multiple addend floating point summation function in a vector microprocessor