|
US2014281413A1
|
|
Superforwarding Processor
|
|
US2014258667A1
|
|
Apparatus and Method for Memory Operation Bonding
|
|
US2014258624A1
|
|
Apparatus and method for operating a processor with an operation cache
|
|
US2014258697A1
|
|
Apparatus and Method for Transitive Instruction Scheduling
|
|
US2014250289A1
|
|
Branch Target Buffer With Efficient Return Prediction Capability
|
|
US2014245317A1
|
|
Resource sharing using process delay
|
|
US2014244987A1
|
|
Precision Exception Signaling for Multiple Data Architecture
|
|
US2014244977A1
|
|
Deferred Saving of Registers in a Shared Register Pool for a Multithreaded Microprocessor
|
|
WO2013090389A1
|
|
Vector size agnostic single instruction multiple data (simd) processor architecture
|
|
GB201409727D0
|
|
Processor with kernel mode access to user space virtual addresses
|
|
US2013061060A1
|
|
Systems and Methods for Controlling the Use of Processing Algorithms, and Applications Thereof
|
|
WO2012177982A1
|
|
Apparatus and method for accelerated hardware page table walk
|
|
WO2012174343A1
|
|
Apparatus and method for hardware initiation of emulated instructions
|
|
WO2012174346A1
|
|
Programmable memory address segments
|
|
CN102346688A
|
|
System and method for automatic hardware interrupt handling
|
|
CN102200905A
|
|
Microprocessor with compact instruction set architecture
|
|
CN101887357A
|
|
Variable register in the instruction set architecture and digital section coding immediately
|
|
US2010312991A1
|
|
Microprocessor with Compact Instruction Set Architecture
|
|
WO2010088129A1
|
|
System and method for improving memory transfer
|
|
CN102077195A
|
|
Microprocessor with compact instruction set architecture
|
