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CA2471255A1
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Timing control in data receivers and transmitters
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Timing control in data receivers and transmitters
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Channel equalisation in data receivers
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Timing recovery in data communication circuits
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Timing recovery in data communication circuits
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A data receiver
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Compensation for interference in data receivers
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Compensation for interference in data receivers
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Processing of quinary data
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Data receiver
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Processing of quinary data
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Echo and crosstalk cancellation
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An address generation unit
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An address generation unit
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DSP coprocessor having control flags mapped to a dual port section of memory for communicating with the host
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