LEVEL 5 NETWORKS INC has a total of 43 patent applications. Its first patent ever was published in 2003. It filed its patents most often in United Kingdom, WIPO (World Intellectual Property Organization) and EPO (European Patent Office). Its main competitors in its focus markets digital networks, computer technology and machines are TIANJIN OPZOON INFORMATION TECHNOLOGY CO LTD, SYSCOM COMP ENGINEERING CO and DALIAN TNET NETWORK TECHNOLOGY CO LTD.
# | Country | Total Patents | |
---|---|---|---|
#1 | United Kingdom | 18 | |
#2 | WIPO (World Intellectual Property Organization) | 16 | |
#3 | EPO (European Patent Office) | 3 | |
#4 | Taiwan | 3 | |
#5 | China | 2 | |
#6 | United States | 1 |
# | Industry | |
---|---|---|
#1 | Digital networks | |
#2 | Computer technology | |
#3 | Machines | |
#4 | Telecommunications |
# | Technology | |
---|---|---|
#1 | Digital information transmission | |
#2 | Electric digital data processing | |
#3 | Unspecified technologies | |
#4 | Multiplex communication |
# | Name | Total Patents |
---|---|---|
#1 | Riddoch David | 11 |
#2 | Riddoch David James | 11 |
#3 | Roberts Derek | 10 |
#4 | Yu Ching | 10 |
#5 | Pope Steve Leslie | 8 |
#6 | Pope Steve | 6 |
#7 | Roberts Derek Edward | 6 |
#8 | Riddoch David J | 4 |
#9 | Chu Der-Ren | 4 |
#10 | Chiang John Mingyung | 4 |
Publication | Filing date | Title |
---|---|---|
GB0802126D0 | Scalable sockets | |
GB0723422D0 | Virtualised receive side scaling | |
GB0709122D0 | Data protocol | |
WO2007091034A1 | Method and apparatus for multicast packet reception | |
GB0621774D0 | Driver level segmentation | |
EP1875708A2 | Data processing system | |
GB0602033D0 | Data buffering | |
GB0600417D0 | Virtualisation support | |
GB0526519D0 | Processing received data | |
GB0519283D0 | Encryption | |
GB0512532D0 | Processing network traffic | |
GB0512537D0 | Data transfer | |
GB0512536D0 | Data transfer | |
GB0512534D0 | Fragmenting data units | |
GB0512533D0 | Signal handling | |
GB0512535D0 | Data transfer | |
GB0512425D0 | Forwarding instructions | |
US2006288129A1 | DMA descriptor queue read and cache write pointer arrangement | |
GB0512219D0 | Processing data | |
GB0519166D0 | Data transmission with constant data rate |