WO9935581A1
|
|
Cache coherence unit with integrated message passing and memory protection for a distributed, shared memory multiprocessor system
|
WO9642053A1
|
|
Method and apparatus for detecting memory addressing errors
|
WO9642054A1
|
|
Method, system and apparatus for efficiently generating binary numbers for testing storage devices
|
WO9638783A1
|
|
Method and apparatus for rotating active instructions in a parallel data processor
|
WO9638789A2
|
|
Programmable instruction trap system and method
|
EP0730220A2
|
|
Method and apparatus for rapid execution of control transfer instructions
|
WO9627832A1
|
|
Parallel access micro-tlb to speed up address translation
|
US5615161A
|
|
Clocked sense amplifier with positive source feedback
|
WO9625705A1
|
|
Structure and method for high-performance speculative execution processor providing special features
|
EP0727736A2
|
|
Method and apparatus for efficiently writing results to renamed registers
|
US5570036A
|
|
CMOS buffer circuit having power-down feature
|
US5541528A
|
|
CMOS buffer circuit having increased speed
|
US5740414A
|
|
Method and apparatus for coordinating the use of physical registers in a microprocessor
|
US5619153A
|
|
Fast swing-limited pullup circuit
|
US5652580A
|
|
Method and apparatus for detecting duplicate entries in a look-up table
|
US5644742A
|
|
Processor structure and method for a time-out checkpoint
|
US5533035A
|
|
Error detection and correction method and apparatus
|
US5638312A
|
|
Method and apparatus for generating a zero bit status flag in a microprocessor
|
US5632028A
|
|
Hardware support for fast software emulation of unimplemented instructions
|
US5680566A
|
|
Lookaside buffer for inputting multiple address translations in a computer system
|