| # | Country | Total Patents | |
|---|---|---|---|
| #1 | United States | 6 | |
| #2 | Australia | 3 | |
| #3 | Germany | 3 | |
| #4 | France | 2 | |
| #5 | United Kingdom | 2 | |
| #6 | Canada | 1 | |
| #7 | EPO (European Patent Office) | 1 | |
| #8 | WIPO (World Intellectual Property Organization) | 1 |
| # | Industry | |
|---|---|---|
| #1 | Computer technology | |
| #2 | Audio-visual technology |
| # | Technology | |
|---|---|---|
| #1 | Electric digital data processing | |
| #2 | Special information storage | |
| #3 | Image data processing |
| # | Name | Total Patents |
|---|---|---|
| #1 | Frank Steven J | 10 |
| #2 | Namias Charles S | 5 |
| #3 | Briggs Karen A | 5 |
| #4 | Bartlett John R | 5 |
| #5 | Schanin David J | 5 |
| #6 | Ely Jonathan C | 5 |
| #7 | Corbin Stephen S | 5 |
| #8 | Zopf David W | 5 |
| #9 | Rossi Arthur M | 5 |
| #10 | Moore Russell L | 4 |
| Publication | Filing date | Title |
|---|---|---|
| US5469037A | Linear accelerated device | |
| US5146607A | Method and apparatus for sharing information between a plurality of processing units | |
| EP0251686A2 | Method and apparatus for sharing information between a plurality of processing units | |
| US4755930A | Hierarchical cache memory system and method | |
| US5067071A | Multiprocessor computer system employing a plurality of tightly coupled processors with interrupt vector bus |