Detecting overflow conditions for negative quotients in nonrestoring two's complement division
US5732243A
Branch processing unit with target cache using low/high banking to support split prefetching
US5784589A
Distributed free register tracking for register renaming using an availability tracking register associated with each stage of an execution pipeline
US5838897A
Debugging a processor using data output during idle bus cycles
US5835967A
Adjusting prefetch size based on source of prefetch address
US5692168A
Prefetch buffer using flow control bit to identify changes of flow within the code stream
US5706491A
Branch processing unit with a return stack including repair using pointers from different pipe stages
US5740416A
Branch processing unit with a far target cache accessed by indirection from the target cache
US5732253A
Branch processing unit with target cache storing history for predicted taken branches and history cache storing history for predicted not-taken branches
US5596735A
Circuit and method for addressing segment descriptor tables
US5805879A
In a pipelined processor, setting a segment access indicator during execution stage using exception handling
US5742755A
Error-handling circuit and method for memory address alignment double fault
US5734844A
Bidirectional single-line handshake with both devices driving the line in the same state for hand-off
US5742184A
Microprocessor having a compensated input buffer circuit
US5777500A
Multiple clock source generation with independently adjustable duty cycles
US5689454A
Circuitry and methodology for pulse capture
US5734881A
Detecting short branches in a prefetch buffer using target location information in a branch target cache
US5701448A
Detecting segment limit violations for branch target when the branch unit does not supply the linear address
US5740410A
Static clock generator
US5615402A
Unified write buffer having information identifying whether the address belongs to a first write operand or a second write operand having an extra wide latch
