|
CN103955410A
|
|
Interruption control method based on multiple interrupt source priority ordering
|
|
CN103810117A
|
|
Instruction storage system for processor
|
|
CN103810122A
|
|
Cache for embedded system
|
|
CN103810116A
|
|
Instruction storage device for embedded system
|
|
CN103399829A
|
|
High-reliability random access memory system
|
|
CN103389924A
|
|
ECC (Error Correction Code) storage system applied to random access memory
|
|
CN103389923A
|
|
Random access memory access bus ECC (error checking and correcting) verification device
|
|
CN103389922A
|
|
Bus ECC (Error Correction Code) checking system for random access memory
|
|
CN103268278A
|
|
SRAM (Static Random Access Memory) controller for supporting multi-core processors and tracking information processing method thereof
|
|
CN103310851A
|
|
Self-repairing SRAM (Static Random Access Memory) controller design for DTMB (Digital Terrestrial Multimedia Broadcasting) demodulation chip
|
|
CN103345910A
|
|
Single-port color palette SRAM controller and control method thereof
|
|
CN103246624A
|
|
Weighted priority scheduling method for multi-interface SRAM (static random access memory)
|
|
CN103116551A
|
|
Nor FLASH memory interface module applied to configurable logic block (CLB) bus
|
|
CN103235760A
|
|
CLB-bus-based NorFLASH memory interface chip with high utilization ratio
|
|
CN103064640A
|
|
Fast read-write method for nandflash memory device
|
|
CN104598169A
|
|
High-reliability data reading method used for flash memorizer
|
|
CN104599717A
|
|
Flash memory data storage method with error correction function
|
|
CN103049408A
|
|
Multi-interface SRAM (static random access memory) read-write control circuit and multi-interface SRAM read-write control method
|
|
CN103020535A
|
|
Data encryption and decryption system with comparing function
|
|
CN102831028A
|
|
ECC (error correction code) error correction method and system based on data bus
|
