|
US2014095778A1
|
|
Methods, systems and apparatus to cache code in non-volatile memory
|
|
US2013346781A1
|
|
Power gating functional units of a processor
|
|
US2014122845A1
|
|
Overlapping atomic regions in a processor
|
|
US2012185714A1
|
|
Method, apparatus, and system for energy efficiency and energy conservation including code recirculation techniques
|
|
US2013013864A1
|
|
Memory access monitor
|
|
US2012297131A1
|
|
Scheduling-Policy-Aware DRAM Page Management Mechanism
|
|
US2012290793A1
|
|
Efficient tag storage for large data caches
|
|
US2012221785A1
|
|
Polymorphic Stacked DRAM Memory Architecture
|
|
US2012162237A1
|
|
Bundle-based CPU/GPU memory controller coordination mechanism
|
|
US2012124563A1
|
|
Compiler support technique for hardware transactional memory systems
|
|
US2012124297A1
|
|
Coherence domain support for multi-tenant environment
|
|
US2012079491A1
|
|
Thread criticality predictor
|
|
US2012054760A1
|
|
Memory request scheduling based on thread criticality
|
|
US2012036512A1
|
|
Enhanced shortest-job-first memory request scheduling
|
|
US2011307689A1
|
|
Processor support for hardware transactional memory
|
|
US2011302586A1
|
|
Multithread application-aware memory scheduling scheme for multi-core processors
|
|
US2011276973A1
|
|
Method and apparatus for scheduling for multiple memory controllers
|
|
US2011276972A1
|
|
Memory-controller-parallelism-aware scheduling for multiple memory controllers
|
|
US2011276974A1
|
|
Scheduling for multiple memory controllers
|
|
US2011209151A1
|
|
Automatic suspend atomic hardware transactional memory in response to detecting an implicit suspend condition and resume thereof
|
